Senior IC Layout Designer – Power Management

About the role

Analog Devices is seeking a Senior IC Layout Designer to create high‑quality section‑level to top‑level layouts for Power Management ICs (PMICs). You will work closely with schematic designers, technology leaders, and other layout engineers to shape design decisions from concept through silicon evaluation.

Key responsibilities

• Develop section‑level and top‑level layouts for PMICs, ensuring precise matching, low parasitics, and minimal IR drop.
• Collaborate with cross‑functional teams to define specifications, drive schedules, and meet analog performance targets.
• Influence product direction by providing layout‑dependent insights and making trade‑off decisions.
• Lead block‑layout resources when required, allocating work, setting timelines, and guiding execution.
• Mentor new hires or interns and contribute to continuous‑improvement initiatives within the layout team.

Required profile

• Extensive experience in multi‑hierarchical (section) layout; top‑chip level layout is a plus.
• Strong fundamentals in semiconductor device physics, layout principles, IC reliability, and failure mechanisms.
• Bachelor’s degree in Electronics or Electrical Engineering.
• At least 4 years of relevant IC layout experience.
• Excellent communication and leadership skills; ability to work with global, cross‑functional teams.

Required skills

• Proficiency with Cadence Virtuoso XL.
• Experience using Calibre verification tools (advantageous).
• Knowledge of Power Management IC blocks such as voltage/current monitors, voltage references, LDOs, and DC‑DC converters.
• Familiarity with 0.18 µm and 90 nm technology nodes.