Integration Design Engineer – Fullchip IP Integration

About the role

Lattice Semiconductor is seeking an Integration Design Engineer to join its Silicon Integration Team in the Philippines. The engineer will be responsible for integrating various IP blocks to create a complete chip, delivering models, views, and collateral to functional teams, and ensuring all checks and simulations are completed for sign‑off.

Key responsibilities

• Collaborate with Architecture, SW, IP Design, and Physical Design teams to generate a full‑chip logical floorplan and behavioral model.
• Design and implement custom and digital density‑specific IPs (e.g., clock networks) and sectors suitable for full‑chip integration.
• Perform full‑chip flows and checks including synthesis, equivalence, DFT, timing closure, power and performance analysis.
• Debug and resolve issues with other functional teams and conduct tape‑out gating audits such as EM/IR analysis, NetERC, PDN extraction, SSO simulations, and ESD checks.

Required profile

• BS or MS in Electronics, Computer, or Electrical Engineering.
• Minimum 5 years of proven experience in custom and digital design implementation.

Required skills

• Proficiency in Verilog and SystemVerilog.
• Experience with FPGA/CPLD design and integration (plus).
• Custom design flow knowledge, including Cadence Virtuoso and SPICE simulations.
• Digital design flow expertise: RTL coding, lint, synthesis, equivalence check, STA using tools such as Xcelium, Genus, Innovus, Tempus.
• Understanding of DFT flow and ATPG generation (plus).
• Scripting skills in Perl, TCL, Shell, Skill, Phyton.